1. Field of the Invention
The present invention relates to a method and structure for improving the adhesion within bonding pads in a semiconductor integrated circuit.
2. Description of the Related Art
As electrical components are made smaller, various strategies have been adopted to reduce the amount of space devoted to connections between the chip containing the integrated circuit devices and the printed circuit board on which the chips are mounted. Electrical connections between integrated circuits on a chip and the printed circuit board are made through bonding pads typically provided at the periphery of the chip. Bonding pad structures may include a bonding metal layer and a barrier metal layer deposited over an underlying dielectric layer such as silicon oxide. The bonding metal layer is in electrical contact with one or more semiconductor devices in the chip. The barrier metal layer on the underlying dielectric layer helps adhere the bonding metal layer, typically aluminum, to the underlying dielectric layer. Conventional bonding pad structures have been observed to delaminate or have layers that separate from one another in response to external forces like those applied in wire bonding processes of the type typically used attaching wires to the bonding pads.
Connections between the bonding pads of a chip and the leads printed on the circuit board have conventionally been provided through the lead frame used as part of lead frame packaging methods. In such lead frame packaging methods, the chip is mounted to a frame which incorporates an array of electrical leads, with thin bonding wires connecting the bonding pads to the electrical leads on the lead frame. The entire chip and lead frame assembly is encapsulated in plastic and then mounted on the printed circuit board through the leads extending from the package. Variations on this basic structure have been introduced over the years. Gang bonding, which attaches multiple leads to multiple bonding pads in a single process step, has been facilitated by adoption of tape automated bonding (TAB) methods, in which some or all of the lead frame is replaced by leads printed on an insulating tape. The chip is attached to the tape at least through bonds between the tape leads and the chip's bonding pads and the chip and the tape assembly is encapsulated within the plastic package in a manner similar to that used with the lead frame. In another variation, the lead frame may be incorporated within a preformed portion of a package, such as a ceramic substrate or header, on which the chip is mounted and which forms a portion of the completed package.
An important advantage of lead frame packaging methods and variations on the lead frame packing methods is the protection provided to the chips by such a package. By connecting the bonding pads to the lead frame through bonding wires or leads, the bonding pads and the chip itself are isolated from external stresses after the initial assembly process. The plastic encapsulation protects the chip and stabilizes the connections between the bonding pads and the leads. Conventional lead frame packaging also has disadvantages. Forming lead frame packages is a complicated and therefore expensive process, so that providing the package is a considerable cost component for low price integrated circuit chips. It is thus desirable to reduce the costs associated with incorporating chips into printed circuit board based circuits. In some applications, the amount of space consumed by the lead frame and plastic package is unacceptable and prevents desired miniaturization of the printed circuit board assembly. For these applications, it is desirable to reduce the space consumed by the chip's packaging, so that the surface area of the printed circuit board devoted to the chip more closely matches the size of the chip.
Chip-on-board methods, where the semiconductor chip is mounted directly to the printed circuit board, have significant space and weight advantages over conventional lead frame packaging methods. Electrical connections between the bonding pads of the chip and the circuit board on which the chip is mounted are typically provided by wire bonding thin wires between the chips bonding pads and the leads printed on the board. The wire bonds may be formed using a variety of techniques including ultrasonic bonding and thermocompression bonding. Ultrasonic bonding uses ultrasonic waves or vibration to attach the wire to the bonding pad. Thermocompression bonding uses a combination of elevated temperature and compressive force to attach the wire to the bonding pad. Both of these bonding techniques impart mechanical and/or thermal energy directly to the bonding pad area and so can damage the bonding pad and the chip. Proper control of the process variables used in these techniques, such as bonding temperature, bonding load and ultrasonic vibration magnitude is important to the formation of high quality bonds and to the protection of the underlying chip.
It has been observed that wire bonding may cause the bonding pad to lift off or peel back (delaminate) from one or more of the underlying layers, weakening the bonding pad structure and damaging other portions of the chip's wiring. Such peel back reduces or prevents electrical contact between the bonding pad and the integrated circuit devices on the chip, which decreases the reliability and reduces the life of the chip. The stresses applied during wire bonding processes are much harder to control for chip-on-board assembly methods than for more conventional lead frame packaging technique for a number of reasons. For example, there are far greater variations in the thickness of printed circuit boards than there are in lead frames. Thus, for chip-on-board methods, there are greater variations in the position of the bonding pad with respect to the wire bonding equipment and so an increased likelihood that an appropriate level of force will be applied during wire bonding. In addition, the flexibility of the circuit board and the comparative inability of the circuit board to dissipate heat significantly increases the stresses associated with chip-on-board wire bonding processes as compared to those used in lead frame packaging techniques.
It is desirable to form bonding pad structures exhibiting improved durability with better adhesion to underlying layers, so that the bonding pad structures are more compatible with chip-on-board techniques.